US 11,930,679 B2
Array substrate, preparation method therefor, and display device
Jingang Fang, Beijing (CN); Luke Ding, Beijing (CN); Jun Liu, Beijing (CN); Bin Zhou, Beijing (CN); and Jun Cheng, Beijing (CN)
Assigned to HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/264,283
Filed by Hefei Xinsheng Optoelectronics Technology Co., Ltd., Hefei (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed May 12, 2020, PCT No. PCT/CN2020/089820
§ 371(c)(1), (2) Date Jan. 28, 2021,
PCT Pub. No. WO2020/233453, PCT Pub. Date Nov. 26, 2020.
Claims priority of application No. 201910412086.1 (CN), filed on May 17, 2019.
Prior Publication US 2021/0296406 A1, Sep. 23, 2021
Int. Cl. H10K 59/35 (2023.01); H01L 27/12 (2006.01); H10K 50/86 (2023.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/123 (2023.01); H10K 59/124 (2023.01); H10K 71/00 (2023.01)
CPC H10K 59/353 (2023.02) [H10K 50/865 (2023.02); H10K 59/1213 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a substrate comprising a plurality of sub-pixel regions and a plurality of monochromatic light-emitting regions;
a thin film transistor located in each of the sub-pixel regions on the substrate, and the thin film transistor comprises a gate, an active layer, and a source-drain electrode;
a passivation layer located on a side, away from the substrate, of the thin film transistor;
a color resist located on a side, away from the substrate, of the passivation layer and located in the monochromatic light-emitting regions;
a planarization layer located on a side, away from the substrate, of the color resist and the passivation layer;
an anode located on a side, away from the substrate, of the planarization layer and electrically connected to a drain electrode in the source-drain electrode through a first through hole penetrating through the passivation layer and the planarization layer; and
dielectric layers located between the source-drain electrode and the substrate, wherein a thickness of at least one of the dielectric layers between the first through hole and the substrate is greater than a thickness of the at least one of the dielectric layers between the color resist and the substrate;
wherein the dielectric layers comprise: a buffer layer located between the substrate and the thin film transistor, and a thickness of the buffer layer between the thin film transistor and the substrate is greater than a thickness of the buffer layer between the color resist and the substrate.