US 11,930,647 B2
Electronic device and method for manufacturing electronic device
Si Jung Yoo, Seoul (KR); Tae Hoon Kim, Seongnam (KR); and Hyung Dong Lee, Suwon (KR)
Assigned to SK hynix Inc., Icheon (KR)
Filed by SK hynix Inc., Icheon (KR)
Filed on Aug. 1, 2022, as Appl. No. 17/878,678.
Application 17/878,678 is a continuation of application No. 16/860,686, filed on Apr. 28, 2020, granted, now 11,437,437.
Claims priority of application No. 10-2019-0109131 (KR), filed on Sep. 3, 2019.
Prior Publication US 2022/0367567 A1, Nov. 17, 2022
Int. Cl. H10B 63/00 (2023.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01); H10N 70/00 (2023.01)
CPC H10B 63/845 (2023.02) [H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02); H10N 70/066 (2023.02); H10N 70/841 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A method of manufacturing an electronic device including a semiconductor memory, the method comprising:
forming a stacked structure including sacrificial layers and insulating layers stacked alternately with each other;
forming conductive pillars passing through the stacked structure;
forming a slit passing through the stacked structure;
forming openings by partially removing the sacrificial layers through the slit;
forming variable resistance layers in the openings;
forming conductive layers in the openings; and
forming material layers including conductive areas and insulating areas by applying an electric field to portions of the sacrificial layers.