US 11,930,590 B2
Stress relief for flip-chip packaged devices
Tianyi Luo, Allen, TX (US); Osvaldo Jorge Lopez, Annandale, NJ (US); Jonathan Almeria Noquil, Plano, TX (US); Satyendra Singh Chauhan, Murphy, TX (US); and Bernardo Gallegos, McKinney, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Mar. 31, 2021, as Appl. No. 17/218,792.
Claims priority of provisional application 63/132,910, filed on Dec. 31, 2020.
Prior Publication US 2022/0210911 A1, Jun. 30, 2022
Int. Cl. H05K 1/02 (2006.01); H01L 21/50 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 21/60 (2006.01)
CPC H05K 1/0271 (2013.01) [H01L 21/50 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/14 (2013.01); H01L 2021/60097 (2013.01); H01L 2224/16225 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a package substrate having a planar die mount surface;
recesses extending into the planar die mount surface; and
a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses, wherein the package substrate is a metal lead frame made entirely of metal.