US 11,929,762 B2
Low density parity check decoder and storage device
Kangseok Lee, Seoul (KR); Geunyeong Yu, Seongnam-si (KR); Youngjun Hwang, Osan-si (KR); Hongrak Son, Anyang-si (KR); Junho Shin, Suwon-si (KR); Bohwan Jun, Seoul (KR); and Hyunseung Han, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 1, 2022, as Appl. No. 17/878,431.
Claims priority of application No. 10-2021-0162955 (KR), filed on Nov. 24, 2021; and application No. 10-2022-0008006 (KR), filed on Jan. 19, 2022.
Prior Publication US 2023/0163785 A1, May 25, 2023
Int. Cl. H03M 13/11 (2006.01)
CPC H03M 13/1137 (2013.01) [H03M 13/112 (2013.01); H03M 13/1134 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the variable nodes updated with reference to an irregular parity check matrix as decoded messages, comprising:
a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes; and
a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.