US 11,929,758 B2
Successive approximation register analog-to-digital converter for wide sampling rate
Jung Won Lee, Seoul (KR); and Ji Hyung Kim, Yongin-si (KR)
Assigned to SEMISOLUTION CO., LTD., Yongin-si (KR)
Appl. No. 17/433,031
Filed by SEMISOLUTION CO., LTD., Yongin-si (KR)
PCT Filed Mar. 19, 2021, PCT No. PCT/KR2021/003393
§ 371(c)(1), (2) Date Aug. 23, 2021,
PCT Pub. No. WO2022/019434, PCT Pub. Date Jan. 27, 2022.
Claims priority of application No. 10-2020-0090579 (KR), filed on Jul. 21, 2020.
Prior Publication US 2023/0344439 A1, Oct. 26, 2023
Int. Cl. H03M 1/38 (2006.01); H03M 1/46 (2006.01)
CPC H03M 1/38 (2013.01) [H03M 1/46 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An analog switch circuit in a successive approximation register analog-to-digital converter for a wide sampling rate, the analog switch circuit comprising:
a first PMOS switch having one end connected to a capacitor and an opposite end connected to a first control node and controlled by a voltage of a second control node;
a second PMOS switch having one end connected to the first control node and an opposite end connected to a reference voltage source configured to output a reference voltage and controlled by a control voltage;
a first control switch unit configured to control a voltage of the first control node and the voltage of the second control node;
a first NMOS switch having one end connected to the capacitor and an opposite end connected to a third control node and controlled by a voltage of a fourth control node;
a second NMOS switch having one end connected to the third control node and an opposite end connected to a ground and controlled by the control voltage; and
a second control switch unit configured to control a voltage of the third control node and the voltage of the fourth control node.