CPC H03M 1/38 (2013.01) [H03M 1/46 (2013.01)] | 10 Claims |
1. An analog switch circuit in a successive approximation register analog-to-digital converter for a wide sampling rate, the analog switch circuit comprising:
a first PMOS switch having one end connected to a capacitor and an opposite end connected to a first control node and controlled by a voltage of a second control node;
a second PMOS switch having one end connected to the first control node and an opposite end connected to a reference voltage source configured to output a reference voltage and controlled by a control voltage;
a first control switch unit configured to control a voltage of the first control node and the voltage of the second control node;
a first NMOS switch having one end connected to the capacitor and an opposite end connected to a third control node and controlled by a voltage of a fourth control node;
a second NMOS switch having one end connected to the third control node and an opposite end connected to a ground and controlled by the control voltage; and
a second control switch unit configured to control a voltage of the third control node and the voltage of the fourth control node.
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