US 11,929,756 B2
System and method for offset calibration in a successive approximation analog to digital converter
Yong Liu, Irvine, CA (US); Jun Cao, Irvine, CA (US); and Delong Cui, Irvine, CA (US)
Assigned to Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed by AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED, Singapore (SG)
Filed on Mar. 14, 2022, as Appl. No. 17/694,225.
Prior Publication US 2023/0291411 A1, Sep. 14, 2023
Int. Cl. H03M 1/10 (2006.01); H03M 1/12 (2006.01); H03M 1/46 (2006.01)
CPC H03M 1/1028 (2013.01) [H03M 1/1009 (2013.01); H03M 1/1245 (2013.01); H03M 1/46 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a sample and digital to analog conversion (DAC) circuit to sample an input voltage to obtain a first sampled voltage;
a first comparator coupled to the sample and DAC circuit;
a first set of storage circuits coupled to the first comparator and the sample and DAC circuit, the first set of storage circuits being configured to store a first subset of a plurality of bits corresponding to the input voltage;
a second comparator coupled to the sample and DAC circuit;
a second set of storage circuits coupled to the second comparator and the sample and DAC circuit, the second set of storage circuits being configured to store a second subset of the plurality of bits corresponding to the input voltage; and
a calibration circuit configured to receive a first bit from a first storage unit of the first set of storage circuits and a number of bits from the first set of storage circuits and the second set of storage circuits, wherein the calibration circuit is configured to provide a first offset signal to control a first offset associated with the first comparator and a second offset signal to control a second offset associated with the second comparator.