CPC H01L 29/66545 (2013.01) [H01L 21/0274 (2013.01); H01L 21/0337 (2013.01); H01L 21/3065 (2013.01); H01L 21/3086 (2013.01); H01L 21/31122 (2013.01); H01L 21/3212 (2013.01); H01L 21/32136 (2013.01); H01L 21/76832 (2013.01); H01L 29/4236 (2013.01); H01L 29/66553 (2013.01); H01L 29/7851 (2013.01); H01L 29/7848 (2013.01)] | 20 Claims |
1. A method, comprising:
forming a semiconductor fin on a substrate;
forming a dielectric layer over the semiconductor fin;
forming a metal gate electrode in the dielectric layer and extending across the semiconductor fin;
forming a source/drain regions on the semiconductor fin and on opposite sides of the metal gate electrode;
performing a first non-zero bias plasma etching process to the metal gate electrode; and
after performing the first non-zero bias plasma etching process, performing a first zero bias plasma etching process to the metal gate electrode.
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