US 11,929,422 B2
Passivation layers for semiconductor devices
Cheng-Yi Peng, Taipei (TW); Ching-Hua Lee, Hsinchu (TW); and Song-Bor Lee, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 29, 2022, as Appl. No. 17/876,816.
Application 17/876,816 is a division of application No. 16/807,305, filed on Mar. 3, 2020, granted, now 11,695,055.
Prior Publication US 2022/0384613 A1, Dec. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66439 (2013.01) [H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate:
first and second source/drain (S/D) regions disposed on the substrate, wherein each of the first and second S/D regions comprises a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers;
nanostructured channel regions disposed between the first and second S/D regions;
a passivation layer, wherein a first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions and
a nanosheet (NS) structure wrapped around the nanostructured channel regions.