US 11,929,420 B2
Power semiconductor devices having multilayer gate dielectric layers that include an etch stop/field control layer and methods of forming such devices
Daniel J. Lichtenwalner, Raleigh, NC (US)
Assigned to Wolfspeed, Inc., Durham, NC (US)
Filed by Wolfspeed, Inc., Durham, NC (US)
Filed on Feb. 10, 2022, as Appl. No. 17/668,448.
Application 17/668,448 is a continuation of application No. 16/922,192, filed on Jul. 7, 2020, granted, now 11,563,101.
Prior Publication US 2022/0165862 A1, May 26, 2022
Int. Cl. H01L 29/51 (2006.01); H01L 29/16 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/513 (2013.01) [H01L 29/1608 (2013.01); H01L 29/401 (2013.01); H01L 29/7803 (2013.01); H01L 29/7813 (2013.01); H01L 29/517 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor layer structure that comprises silicon carbide, the semiconductor layer structure comprising a source region and a trench formed in the semiconductor layer structure, where at least some corners of the trench are rounded;
a gate dielectric layer on a top surface of the source region and within the trench, the gate dielectric layer comprising lower corners and upper corners, where at least one of the lower corners and upper corners comprises a rounded corner;
a gate electrode on the gate dielectric layer opposite the semiconductor layer structure; and
a dielectric isolation pattern on the gate electrode and the gate dielectric layer,
wherein the gate dielectric layer extends laterally beyond sidewalls of the gate electrode and sidewalls of the dielectric isolation pattern.