US 11,929,415 B2
Thin film transistors with offset source and drain structures and process for forming such
Chieh-Jen Ku, Hillsboro, OR (US); Pei-Hua Wang, Beaverton, OR (US); Bernhard Sell, Portland, OR (US); and Travis W. Lajoie, Forest Grove, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 20, 2019, as Appl. No. 16/447,880.
Prior Publication US 2020/0403076 A1, Dec. 24, 2020
Int. Cl. H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H10B 12/00 (2023.01)
CPC H01L 29/42384 (2013.01) [H01L 29/41733 (2013.01); H01L 29/41775 (2013.01); H01L 29/66742 (2013.01); H10B 12/00 (2023.02); H10B 12/01 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A device, comprising:
a source contact and a drain contact;
a first dielectric between the source contact and the drain contact, the first dielectric having an uppermost surface at a same level as an uppermost surface of the source contact and the drain contact;
a channel under the source contact and the drain contact;
a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact;
a second dielectric above the gate electrode and underneath the channel; and
an interconnect layer beneath the gate electrode, the interconnect layer extending laterally beyond the source contact and the drain contact along a direction from the source contact to the drain contact.