US 11,929,407 B2
Method of fabricating high electron mobility transistor
Ting-En Hsieh, New Taipei (TW); Yu-Chieh Chou, New Taipei (TW); and Yung-Fong Lin, Taoyuan (TW)
Assigned to Vanguard International Semiconductor Corporation, Hsinchu (TW)
Filed by Vanguard International Semiconductor Corporation, Hsinchu (TW)
Filed on May 30, 2022, as Appl. No. 17/827,809.
Application 17/827,809 is a division of application No. 16/861,191, filed on Apr. 28, 2020, granted, now 11,380,767.
Prior Publication US 2022/0293747 A1, Sep. 15, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/40 (2006.01); H01L 29/47 (2006.01); H01L 29/778 (2006.01)
CPC H01L 29/408 (2013.01) [H01L 21/0214 (2013.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/02178 (2013.01); H01L 21/28581 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/475 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/7787 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method of fabricating a high electron mobility transistor, comprising:
providing a substrate having a group III-V channel layer, a group III-V barrier layer, a group III-V gate layer, and a gate etch stop layer disposed thereon;
forming a passivation layer covering the group III-V barrier layer and the gate etch stop layer;
forming a gate contact hole and at least one source/drain contact hole in the passivation layer, wherein the gate contact hole exposes the gate etch stop layer, and the at least one source/drain contact hole exposes the group III-V channel layer; and
forming a conductive layer conformally disposed on a top surface of the passivation layer and in the gate contact hole and the at least one source/drain contact hole.