US 11,929,398 B2
FinFET structure and method for manufacturing thereof
Chun Hsiung Tsai, Hsinchu County (TW); Lai-Wan Chong, Kaohsiung (TW); Chien-Wei Lee, Hsinchu (TW); and Kei-Wei Chen, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jun. 1, 2021, as Appl. No. 17/335,811.
Application 15/796,060 is a division of application No. 14/600,781, filed on Jan. 20, 2015, granted, now 9,806,154, issued on Oct. 31, 2017.
Application 17/335,811 is a continuation of application No. 15/796,060, filed on Oct. 27, 2017, granted, now 11,450,742.
Prior Publication US 2021/0288146 A1, Sep. 16, 2021
Int. Cl. H01L 29/76 (2006.01); H01L 21/265 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/94 (2006.01)
CPC H01L 29/1037 (2013.01) [H01L 21/26586 (2013.01); H01L 29/0649 (2013.01); H01L 29/1083 (2013.01); H01L 29/66795 (2013.01); H01L 29/66803 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A FinFET structure, comprising:
a substrate;
a fin protruding from the substrate, comprising a first portion and a second portion below the first portion, wherein the first portion comprises a first dopant concentration of a dopant, and the second portion comprises a second dopant concentration of the dopant, the second dopant concentration is greater than the first dopant concentration;
a gate over the fin, wherein the second portion of the fin is below a bottom surface of the gate; and
an insulating layer over the substrate and proximal to the second portion of the fin, wherein at least a first portion of the insulating layer comprises a third dopant concentration of the dopant, the third dopant concentration is greater than the first dopant concentration.