US 11,929,368 B2
Array substrate and display panel
Dongfang Zhao, Langfang (CN); Kookchul Moon, Langfang (CN); Junfeng Li, Langfang (CN); Zhe Du, Langfang (CN); Yong Ge, Langfang (CN); Sha Yuan, Langfang (CN); and Lin Xu, Langfang (CN)
Assigned to Yungu (Gu'an) Technology Co., Ltd., Langfang (CN)
Filed by Yungu (Gu'an) Technology Co., Ltd., Hebei (CN)
Filed on Nov. 4, 2021, as Appl. No. 17/519,222.
Application 17/519,222 is a continuation of application No. PCT/CN2020/105066, filed on Jul. 28, 2020.
Claims priority of application No. 201911192059.4 (CN), filed on Nov. 28, 2019.
Prior Publication US 2022/0059576 A1, Feb. 24, 2022
Int. Cl. H01L 27/12 (2006.01)
CPC H01L 27/1237 (2013.01) [H01L 27/1259 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a thin film transistor array layer, wherein the thin film transistor array layer comprises a driving transistor, a switching transistor and a capacitor,
wherein the driving transistor comprises a first active layer, a first gate insulating layer, a first gate and an insulating dielectric layer sequentially stacked;
the switching transistor comprises a second active layer, a second gate insulating layer and a second gate sequentially stacked; and
the insulating dielectric layer and the second gate insulating layer are located at a same layer; a thickness of the first gate insulating layer is greater than a thickness of the second gate insulating layer; the capacitor comprises a first electrode plate and a second electrode plate, wherein the first electrode plate and the first gate are disposed in a same layer, and the second electrode plate and the second gate are disposed in a same layer.