US 11,929,340 B2
Arrangement of power-grounds in package structures
Ting-Yu Yeh, Hsinchu (TW); Chun-Hua Chang, Zhubei (TW); Fong-Yuan Chang, Hsinchu (TW); and Jyh Chwen Frank Lee, Palo Alto, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 4, 2021, as Appl. No. 17/394,213.
Claims priority of provisional application 63/139,940, filed on Jan. 21, 2021.
Prior Publication US 2022/0230981 A1, Jul. 21, 2022
Int. Cl. H01L 21/56 (2006.01); H01L 23/00 (2006.01)
CPC H01L 24/20 (2013.01) [H01L 24/19 (2013.01); H01L 21/568 (2013.01); H01L 24/13 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/19 (2013.01); H01L 2224/221 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a device die;
an encapsulant encapsulating the device die therein;
a redistribution structure over and electrically connected to the device die, wherein the redistribution structure comprises a bottom layer and a plurality of upper layers over the bottom layer, and wherein the redistribution structure comprises:
a first power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers;
a second power-ground macro extending from the topmost layer in the plurality of upper layers to the bottommost layer in the plurality of upper layers;
at least one first conductive feature in the bottom layer and overlapped by the first power-ground macro; and
at least one second conductive feature in the bottom layer and overlapped by the second power-ground macro, wherein patterns of the at least one first conductive feature are different from the at least one second conductive feature.