US 11,929,329 B2
Damascene process using cap layer
Chia-Cheng Chou, Keelung (TW); Chung-Chi Ko, Nantou (TW); Tze-Liang Lee, Hsinchu (TW); and Ming-Tsung Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 28, 2020, as Appl. No. 16/885,278.
Prior Publication US 2021/0375779 A1, Dec. 2, 2021
Int. Cl. H01L 21/768 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/53295 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76832 (2013.01); H01L 21/76835 (2013.01); H01L 21/76807 (2013.01); H01L 21/7684 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, comprising:
forming an etch stop layer over the substrate, wherein the etch stop layer is a four-layer structure comprising, from bottom to top, AlOxNy, SiCO, AlOx and SiCO;
forming a low-k dielectric layer over etch stop layer;
forming a cap layer on the low-k dielectric layer, wherein a carbon atom content of the cap layer ranges from 20 at % to 35 at % and is greater than a carbon atom content of the low-k dielectric layer;
forming a patterned hard mask layer on the cap layer;
patterning the cap layer and the low-k dielectric layer by using the patterned hard mask layer as a mask, thereby forming an opening in the cap layer and the low-k dielectric layer; and
forming a conductive layer in the opening.