US 11,929,326 B2
Method of forming graphene barrier layer in interconnect structure
Shin-Yi Yang, New Taipei (TW); Ming-Han Lee, Taipei (TW); and Shau-Lin Shue, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Dec. 20, 2021, as Appl. No. 17/556,134.
Prior Publication US 2022/0115327 A1, Apr. 14, 2022
Int. Cl. H01L 23/532 (2006.01); H01L 21/324 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/53238 (2013.01) [H01L 21/324 (2013.01); H01L 21/76876 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first contact feature in a first dielectric layer over a workpiece;
forming a second dielectric layer over the first contact feature and the first dielectric layer;
forming a via opening in the second dielectric layer to expose a portion of the first contact feature;
depositing a seed metal layer in the via opening and over the second dielectric layer;
patterning the seed metal layer to expose a portion of the second dielectric layer;
depositing a third dielectric layer over the exposed portion of the second dielectric layer;
depositing a carbon layer over the seed metal layer and the third dielectric layer; and
annealing the workpiece to form a graphene layer between the seed metal layer and the third dielectric layer.