US 11,929,287 B2
Dielectric liner for field effect transistors
Zhi-Chang Lin, Zhubei (TW); Shih-Cheng Chen, Taipei (TW); Kuo-Cheng Chiang, Zhubei (TW); Kuan-Ting Pan, Taipei (TW); Jung-Hung Chang, Changhua County (TW); Lo-Heng Chang, Hsinchu (TW); and Chien Ning Yao, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 23, 2021, as Appl. No. 17/238,376.
Prior Publication US 2022/0344213 A1, Oct. 27, 2022
Int. Cl. H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/823468 (2013.01) [H01L 29/42392 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a fin bottom portion on the substrate;
a stacked nanostructure comprising a plurality of layers on the fin bottom portion; and
an isolation layer between the stacked nanostructure and the fin bottom portion;
a dielectric liner on a sidewall of the stacked nanostructure and in contact with an end of the stacked nanostructure; and
a spacer structure between the plurality of layers of the stacked nanostructure and in contact with the dielectric liner.