US 11,929,131 B2
Memory device degradation monitoring
Eyal Fayneh, Givatayim (IL); Guy Redler, Haifa (IL); and Evelyn Landman, Haifa (IL)
Assigned to PROTEANTECS LTD., Haifa (IL)
Appl. No. 17/782,146
Filed by PROTEANTECS LTD., Haifa (IL)
PCT Filed Dec. 3, 2020, PCT No. PCT/IL2020/051246
§ 371(c)(1), (2) Date Jun. 2, 2022,
PCT Pub. No. WO2021/111444, PCT Pub. Date Jun. 10, 2021.
Claims priority of provisional application 62/943,322, filed on Dec. 4, 2019.
Prior Publication US 2023/0009637 A1, Jan. 12, 2023
Int. Cl. G11C 11/419 (2006.01); G11C 29/08 (2006.01)
CPC G11C 29/08 (2013.01) [G11C 11/419 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A memory circuit, comprising:
a synchronous memory cell array, configured to receive a clock signal and having address lines and bit lines; and
a margin agent, configured to receive a signal derived from at least one of the bit lines and to determine a status value of the synchronous memory cell array based on a time duration between a transition of the clock signal and a change on the received signal from at least one of the bit lines due to a signaling on at least one of the address lines.