CPC G11C 29/08 (2013.01) [G11C 11/419 (2013.01)] | 22 Claims |
1. A memory circuit, comprising:
a synchronous memory cell array, configured to receive a clock signal and having address lines and bit lines; and
a margin agent, configured to receive a signal derived from at least one of the bit lines and to determine a status value of the synchronous memory cell array based on a time duration between a transition of the clock signal and a change on the received signal from at least one of the bit lines due to a signaling on at least one of the address lines.
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