US 11,929,128 B2
Memory readout circuit and method
Chih-Min Liu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 27, 2023, as Appl. No. 18/190,796.
Application 18/190,796 is a continuation of application No. 17/671,372, filed on Feb. 14, 2022, granted, now 11,615,860.
Application 17/671,372 is a continuation of application No. 17/028,837, filed on Sep. 22, 2020, granted, now 11,270,780, issued on Mar. 8, 2022.
Claims priority of provisional application 63/002,550, filed on Mar. 31, 2020.
Prior Publication US 2023/0238071 A1, Jul. 27, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 17/18 (2006.01); G11C 11/16 (2006.01); G11C 17/16 (2006.01)
CPC G11C 17/18 (2013.01) [G11C 11/1673 (2013.01); G11C 17/16 (2013.01); G11C 11/161 (2013.01); G11C 11/1659 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
an operational amplifier comprising:
an inverting input terminal capacitively coupled to each of a one-time programmable (OTP) cell array and a non-volatile memory (NVM) cell array; and
first and second output terminals;
an analog-to-digital converter (ADC) coupled to the first and second output terminals, thereby configured to receive a differential output voltage from the operational amplifier; and
a comparator coupled to the ADC and configured to output a data bit responsive to a digital output signal received from the ADC,
wherein the circuit is configured to cause the operational amplifier to generate the differential output voltage based on each of a current received from an OTP cell of the OTP cell array and a voltage received from an NVM cell of the NVM cell array.