US 11,929,116 B2
Memory device having a negative voltage circuit
Yi-Hsin Nien, Hsinchu (TW); Hidehiro Fujiwara, Hsinchu (TW); Chih-Yu Lin, Taichung (TW); and Yen-Huei Chen, Jhudong Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 23, 2023, as Appl. No. 18/158,076.
Application 18/158,076 is a continuation of application No. 17/082,404, filed on Oct. 28, 2020, granted, now 11,562,786.
Claims priority of provisional application 62/955,178, filed on Dec. 30, 2019.
Prior Publication US 2023/0162786 A1, May 25, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/419 (2006.01)
CPC G11C 11/419 (2013.01) 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory cell;
a bit line connected to the memory cell;
a negative voltage generator connected to the bit line, wherein the negative voltage generator is operative to provide a first write path for the bit line;
a pull down transistor connected between the bit line and ground; and
a pull down circuit comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the pull down circuit is operative to receive data signal to be written to the memory cell, wherein the second input terminal of the pull down circuit is directly connected to the negative voltage generator and is operative to receive a write assist enable signal that is being provided to the negative voltage generator, wherein the output terminal of the pull down circuit is connected to a gate of the pull down transistor, wherein the pull down circuit is operative to enable the pull down transistor in response to the write assist enable signal attaining a second value, and wherein the pull down transistor is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.