US 11,929,112 B2
Sense amplifier, memory, and method for controlling sense amplifier
Chunyu Peng, Hefei (CN); Zijian Wang, Hefei (CN); Wenjuan Lu, Hefei (CN); Xiulong Wu, Hefei (CN); Jun He, Hefei (CN); Xin Li, Hefei (CN); Zhan Ying, Hefei (CN); Kanyu Cao, Hefei (CN); Zhiting Lin, Hefei (CN); and Junning Chen, Hefei (CN)
Assigned to ANHUI UNIVERSITY, Hefei (CN); and CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by ANHUI UNIVERSITY, Anhui (CN); and CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 13, 2021, as Appl. No. 17/472,792.
Application 17/472,792 is a continuation of application No. PCT/CN2020/139624, filed on Dec. 25, 2020.
Claims priority of application No. 202010733146.2 (CN), filed on Jul. 27, 2020.
Prior Publication US 2022/0028446 A1, Jan. 27, 2022
Int. Cl. G11C 11/4091 (2006.01); G11C 5/06 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 11/4099 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 5/06 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 11/4099 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A sense amplifier, comprising:
an amplification circuit configured to amplify a voltage transmitted by a bit line or a reference bit line, when the sense amplifier is at an amplification stage;
a first switch circuit configured to control the amplification circuit to be disconnected from the reference bit line, when the sense amplifier performs a read operation on the bit line and the sense amplifier is at the amplification stage; and
a discharge control circuit configured to discharge the sense amplifier after the sense amplifier performs a read ‘1’ operation on the bit line.