US 11,929,111 B2
Sense amplifier, memory and method for controlling sense amplifier
Zhiting Lin, Hefei (CN); Guanglei Wen, Hefei (CN); Jun He, Hefei (CN); Zhan Ying, Hefei (CN); Xin Li, Hefei (CN); Kanyu Cao, Hefei (CN); Wenjuan Lu, Hefei (CN); Chunyu Peng, Hefei (CN); Xiulong Wu, Hefei (CN); and Junning Chen, Hefei (CN)
Assigned to ANHUI UNIVERSITY, Hefei (CN); and CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by ANHUI UNIVERSITY, Anhui (CN); and CHANGXIN MEMORY TECHNOLOGIES, INC, Hefei (CN)
Filed on Sep. 10, 2021, as Appl. No. 17/472,157.
Application 17/472,157 is a continuation of application No. PCT/CN2020/139653, filed on Dec. 25, 2020.
Claims priority of application No. 202010902476.X (CN), filed on Sep. 1, 2020.
Prior Publication US 2022/0068357 A1, Mar. 3, 2022
Int. Cl. G11C 5/06 (2006.01); G11C 11/4074 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 5/06 (2013.01); G11C 11/4074 (2013.01); G11C 11/4094 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A sense amplifier, comprising:
an amplification circuit, arranged to read data in a memory cell and comprising a plurality of transistors; and
a control circuit, electrically connected to the amplification circuit and comprising a plurality of switches,
wherein in a first offset compensation stage of the sense amplifier, the control circuit is arranged to control, through controlling on-off states of the plurality of switches by receiving at least one control signal, the plurality of transistors of the amplification circuit to form a first inverter and a second inverter, each of the first inverter and the second inverter being an inverter with an input terminal and an output terminal connected to each other; and
in a second offset compensation stage of the sense amplifier, the control circuit is arranged to control, through controlling the on-off states of the plurality of switches by receiving the at least one control signal, a first part of the plurality of transistors of the amplification circuit to form a current mirror structure,
wherein the plurality of transistors of the amplification circuit comprise:
a first P-channel Metal Oxide Semiconductor (PMOS) transistor;
a second PMOS transistor;
a first N-channel Metal Oxide Semiconductor (NMOS) transistor, a gate of the first NMOS transistor being connected to a first bitline, and a drain of the first NMOS transistor being connected to a drain of the first PMOS transistor through a first node; and
a second NMOS transistor, a gate of the second NMOS transistor being connected to a second bitline, and a drain of the second NMOS transistor being connected to a drain of the second PMOS transistor through a second node,
wherein in the first offset compensation stage of the sense amplifier, the first PMOS transistor and the first NMOS transistor are configured as the first inverter, and the second PMOS transistor and the second NMOS transistor are configured as the second inverter.