CPC G11C 11/4085 (2013.01) [G11C 11/4072 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01)] | 16 Claims |
1. A memory detection method, comprising:
initializing all storage units in a storage unit array;
determining a plurality of target wordlines, wherein two adjacent target wordlines of the plurality of target wordlines are provided with a plurality of interfering wordlines therebetween;
turning on the plurality of target wordlines, and performing a write operation on storage units connected to the plurality of target wordlines;
performing repeatedly turn-on and turn-off of the plurality of interfering wordlines for a plurality of times; and
performing a read operation on the storage units connected to the plurality of target wordlines;
wherein a write operation is performed on storage units connected to the plurality of interfering wordlines by means of forced current sinking;
wherein before the performing repeatedly turn-on and turn-off of the plurality of interfering wordlines for a plurality of times, the method further comprises:
refreshing the storage unit array after performing the write operation on the storage units connected to the plurality of target wordlines; and
performing voltage regulation on all the storage units in the storage unit array to increase a voltage difference between the storage units connected to the plurality of interfering wordlines and the storage units connected to the plurality of target wordlines.
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