| CPC G06N 3/063 (2013.01) [G06N 3/04 (2013.01); G11C 11/54 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01)] | 18 Claims |
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1. A synapse string array configured by arranging a plurality of synapse strings in an array form, wherein the synapse string includes:
first and second cell strings each having a plurality of memory cell elements connected in series; and first switch elements connected to one of both ends of the first and second cell strings, respectively, wherein the memory cell elements of the first cell string and the memory cell elements of the second cell string are in a one-to-one correspondence,
and a pair of the memory cell elements being in a one-to-one correspondence has one terminal electrically connected to each other to constitute one synapse morphic element,
and wherein the terminals electrically connected to each other of the memory cell elements being in a one-to-one correspondence are terminals to which a read voltage or a pass voltage is applied or to which a program voltage or an erase voltage is applied
wherein the plurality of pairs of memory cell elements included in the first and second cell strings of the synapse string constitute a plurality of synapse morphic elements
wherein, the memory cell elements on the same layer in the synapse string array are connected though the word line (WL),
wherein the ends of the first switch elements of the synapse string array are connected in the bit line (BL) direction through the bit line (BL),
wherein the gate (or control gate) electrodes of the firstswitch elements of the synapse string array are connected in the direction of the word line (WL) through a string-select line (SSL),
and wherein the ends of the memory cell elements located at the bottoms of the synapse strings constituting the synapse string array are connected through a source line (SL).
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