US 11,928,512 B2
Quiesce reconfigurable data processor
Raghu Prabhakar, San Jose, CA (US); Manish K. Shah, Austin, TX (US); Pramod Nataraja, San Jose, CA (US); David Brian Jackson, Dana Point, CA (US); Kin Hing Leung, Cupertino, CA (US); Ram Sivaramakrishnan, San Jose, CA (US); Sumti Jairath, Santa Clara, CA (US); and Gregory Frederick Grohoski, Bee Cave, TX (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on May 17, 2021, as Appl. No. 17/322,697.
Application 17/322,697 is a continuation of application No. 16/504,627, filed on Jul. 8, 2019, granted, now 11,055,141.
Prior Publication US 2021/0271519 A1, Sep. 2, 2021
Int. Cl. G06F 9/50 (2006.01); G06F 15/80 (2006.01)
CPC G06F 9/5027 (2013.01) [G06F 15/80 (2013.01); G06F 2209/506 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A computer-implemented method for operating a processing system including an array of configurable processing units, comprising:
configuring a spatially configurable array of configurable processing units for execution of a data processing operation, the data processing operation including a plurality of execution fragments, by configuring a plurality of resource groups of configurable processing units in the array to execute respective execution fragments of the plurality of execution fragments; and
during execution of the data processing operation using the spatially configurable array, responding to a control signal to quiesce the plurality of resource groups on quiesce boundaries of the respective execution fragments.