CPC G06F 9/3806 (2013.01) [G06F 9/3802 (2013.01); G06F 9/3814 (2013.01); G06F 9/382 (2013.01); G06F 9/383 (2013.01); G06F 9/3844 (2013.01); G06F 12/0875 (2013.01); G06F 9/30145 (2013.01); G06F 2212/452 (2013.01)] | 20 Claims |
1. An apparatus comprising:
predecode circuitry to predecode an entry in a cache to generate a predecoded branch operation, the entry being associated with a cold branch operation, wherein the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line; and
a Branch Prefetch Buffer (BPB) to store the predecoded branch operation in response to a cache line fill operation of the cold branch operation in an instruction cache.
|