US 11,928,472 B2
Branch prefetch mechanisms for mitigating frontend branch resteers
Gilles Pokam, Livermore, CA (US); Jared Warner Stark, IV, Portland, OR (US); Niranjan Kumar Soundararajan, Bengaluru (IN); and Oleg Ladin, Kaliningrad (RU)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 26, 2020, as Appl. No. 17/033,771.
Prior Publication US 2022/0100520 A1, Mar. 31, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/0875 (2016.01)
CPC G06F 9/3806 (2013.01) [G06F 9/3802 (2013.01); G06F 9/3814 (2013.01); G06F 9/382 (2013.01); G06F 9/383 (2013.01); G06F 9/3844 (2013.01); G06F 12/0875 (2013.01); G06F 9/30145 (2013.01); G06F 2212/452 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
predecode circuitry to predecode an entry in a cache to generate a predecoded branch operation, the entry being associated with a cold branch operation, wherein the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line; and
a Branch Prefetch Buffer (BPB) to store the predecoded branch operation in response to a cache line fill operation of the cold branch operation in an instruction cache.