US 11,928,416 B2
Semiconductor process technology assessment
Hung-Chih Ou, Kaohsiung (TW); Kuo-Fu Lee, Hsinchu County (TW); Wen-Hao Chen, Hsinchu (TW); Keh-Jeng Chang, Hsinchu (TW); and Hsiang-Ho Chang, Miaoli County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 1, 2023, as Appl. No. 18/176,701.
Application 18/176,701 is a continuation of application No. 17/231,194, filed on Apr. 15, 2021, granted, now 11,604,915.
Prior Publication US 2023/0205974 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/398 (2020.01); G06F 119/18 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 2119/18 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method of process technology assessment, comprising:
defining a scope of the process technology assessment by assessing changes between an original process technology that includes original layout parameters and a first process technology that includes first layout parameters;
modeling a first object in an integrated circuit into a first resistance in the first process technology and a first capacitance in the first process technology;
generating a first resistance scaling factor that is multiplied by an original resistance in the original process technology to provide the first resistance and a first capacitance scaling factor that is multiplied by an original capacitance in the original process technology to provide the first capacitance;
inputting the first resistance scaling factor and the first capacitance scaling factor into an electronic design automation (EDA) tool;
inputting an original technology file corresponding to the original process technology into the EDA tool; and
utilizing, by the EDA tool, the first resistance scaling factor, the first capacitance scaling factor, and the original technology file for the simulation of the integrated circuit.