US 11,928,415 B2
Hard-to-fix (HTF) design rule check (DRC) violations prediction
Ching Hsu, Hsinchu County (TW); Shih-Yao Lin, Hsinchu (TW); and Yi-Lin Chuang, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 23, 2023, as Appl. No. 18/157,988.
Application 18/157,988 is a continuation of application No. 17/140,701, filed on Jan. 4, 2021, granted, now 11,562,118.
Prior Publication US 2023/0229846 A1, Jul. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06N 5/04 (2023.01); G06N 20/00 (2019.01)
CPC G06F 30/398 (2020.01) [G06F 30/392 (2020.01); G06N 5/04 (2013.01); G06N 20/00 (2019.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
training a machine learning model with a plurality of electronic circuit placement layouts;
predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout;
identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and
fixing, by an engineering change order (ECO) tool, the DRC violations,
wherein the training the machine learning model comprises:
extracting a plurality of feature combinations of the plurality of electronic circuit placement layouts;
calculating fix rates of DRC violations present on the plurality of electronic circuit placement layouts;
establishing a relationship between the fix rates and the plurality of feature combinations; and
normalizing the plurality of feature combinations of the plurality of electronic circuit placement layouts.