US 11,928,409 B2
Dynamic abstract generation and synthesis flow with area prediction
Daniel Lewis, Bangalore (IN); and Rahul M Rao, Bangalore (IN)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jan. 3, 2022, as Appl. No. 17/567,328.
Prior Publication US 2023/0214563 A1, Jul. 6, 2023
Int. Cl. G06F 30/30 (2020.01); G06F 30/27 (2020.01); G06F 30/323 (2020.01); G06F 30/327 (2020.01); G06F 30/39 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 30/323 (2020.01); G06F 30/39 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising:
receiving, by a processor, a physical design block and a physical hierarchy of a chip design of a chip;
extracting, by the processor, one or more features of a macro to be added to the chip design based on a logic synthesis of the chip design;
receiving, by the processor, additional constraints as parameters for the macro, the additional constraints including a highest level of metal that can be used by the macro, an optimization option for the macro, a desired aspect ratio of the macro, and an uplift factor of the macro;
predicting, by the processor, specifications of the macro to be added to the chip design based on the physical design block and the additional constraints, the predicting performed using a pre-trained machine learning model;
using, by the processor, the specifications of the macro to perform a physical synthesis of the chip design to determine a physical layout of the chip.