CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
11. A storage device comprising:
a memory controller; and
a first memory device configured to store data under control of the memory controller,
wherein the first memory device comprises:
a first mode register in which a partial array refresh enable setting is set; and
a second mode register configured to store data indicating a non-masking segment that is a target of a partial array refresh, and a masking segment that is not the target of the partial array refresh,
wherein the memory controller is configured to:
receive a refresh command from a host through a host interface;
receive a write command for the masking segment from the host through the host interface; and
store data in the first memory device according to the write command while performing the partial array refresh for the non-masking segment based on the refresh command in the first memory device.
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