US 11,928,357 B2
Method and system for adjusting memory, and semiconductor device
Shu-Liang Ning, Hefei (CN); Jun He, Hefei (CN); Zhan Ying, Hefei (CN); and Jie Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 18, 2022, as Appl. No. 17/577,611.
Application 17/577,611 is a continuation of application No. PCT/CN2021/103838, filed on Jun. 30, 2021.
Claims priority of application No. 202010879444.2 (CN), filed on Aug. 27, 2020.
Prior Publication US 2022/0137872 A1, May 5, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method for adjusting a memory, the memory comprising a transistor, a gate of the transistor being electrically connected to a word line of the memory, one of a pair of source/drain ends of the transistor being electrically connected to a bit line of the memory via a sense amplifier and a second one of the pair of source/drain ends being electrically connected to a storage capacitor of the memory, and the method comprising:
acquiring a mapping relationship among a temperature of the transistor, a substrate bias voltage of a sense amplification transistor in the sense amplifier, and an actual data writing time of the memory;
acquiring a current temperature of the transistor; and
adjusting the substrate bias voltage on a basis of the current temperature and the mapping relationship, such that an actual data writing time corresponding to an adjusted substrate bias is within a preset writing time.