US 11,928,177 B2
Methods and apparatus for performing video processing matrix operations within a memory array
Fa-Long Luo, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 19, 2022, as Appl. No. 17/948,126.
Application 17/948,126 is a continuation of application No. 16/689,981, filed on Nov. 20, 2019, granted, now 11,449,577.
Prior Publication US 2023/0014169 A1, Jan. 19, 2023
Int. Cl. G06F 17/16 (2006.01); G06F 1/03 (2006.01); G06F 12/02 (2006.01); G06F 17/14 (2006.01); G11C 11/4094 (2006.01)
CPC G06F 17/16 (2013.01) [G06F 1/03 (2013.01); G06F 12/0207 (2013.01); G06F 17/147 (2013.01); G11C 11/4094 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a processor coupled to a non-transitory computer readable medium having instructions stored thereon that cause the processor to:
send a matrix transformation opcode to a memory device having an array of memory cells, and a control logic;
wherein a first cell of the array of memory cells is configured to store a first digital value as an analog value;
wherein the control logic is configured to structure the array of memory cells according to the matrix transformation opcode to perform a matrix computation in an analog form; and
wherein a memory sense component of the memory device is coupled to the first memory cell and operable to convert the analog value of the first cell into a second digital value.