CPC G06F 17/16 (2013.01) [G06F 1/03 (2013.01); G06F 12/0207 (2013.01); G06F 17/147 (2013.01); G11C 11/4094 (2013.01)] | 20 Claims |
1. A device comprising:
a processor coupled to a non-transitory computer readable medium having instructions stored thereon that cause the processor to:
send a matrix transformation opcode to a memory device having an array of memory cells, and a control logic;
wherein a first cell of the array of memory cells is configured to store a first digital value as an analog value;
wherein the control logic is configured to structure the array of memory cells according to the matrix transformation opcode to perform a matrix computation in an analog form; and
wherein a memory sense component of the memory device is coupled to the first memory cell and operable to convert the analog value of the first cell into a second digital value.
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