US 11,928,071 B2
System communication technique over PCIe® (peripheral component interconnect express) link
Chuanhua Lei, Singapore (SG); and Jiaxiang Shi, Singapore (SG)
Assigned to MaxLinear, Inc., Carlsbad, CA (US)
Appl. No. 17/594,828
Filed by MAXLINEAR, INC., Carlsbad, CA (US)
PCT Filed Mar. 27, 2020, PCT No. PCT/US2020/025112
§ 371(c)(1), (2) Date Oct. 29, 2021,
PCT Pub. No. WO2020/222951, PCT Pub. Date Nov. 5, 2020.
Claims priority of provisional application 62/839,984, filed on Apr. 29, 2019.
Prior Publication US 2022/0214992 A1, Jul. 7, 2022
Int. Cl. G06F 13/42 (2006.01); G06F 11/07 (2006.01); G06F 13/10 (2006.01)
CPC G06F 13/4221 (2013.01) [G06F 11/0745 (2013.01); G06F 11/0769 (2013.01); G06F 13/102 (2013.01); G06F 2213/0026 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An apparatus configured for a Root Complex (RC) of a PCIe (Peripheral Component Interconnect express) system, comprising:
a memory; and
one or more processors configured to:
generate a PCIe VDM (Vendor Defined Message) message for an EP (Endpoint) of the PCIe system, wherein the PCIe VDM message comprises at least one of: an interrupt trigger for the EP of the PCIe system, information on a reset status at the RC, information on a status of at least one data path, or information on a buffer status.