CPC G06F 12/0607 (2013.01) [G06F 12/04 (2013.01); H04B 17/26 (2015.01); H04B 17/27 (2015.01); H04B 17/318 (2015.01); H04W 4/026 (2013.01); H04W 4/029 (2018.02); H04W 4/33 (2018.02); G06F 9/30134 (2013.01); H04B 17/24 (2015.01); H04L 2101/622 (2022.05); H04L 2101/69 (2022.05); H04W 84/12 (2013.01)] | 23 Claims |
1. A system comprising:
a memory component; and
a processing device operatively coupled with the memory component, the processing device configured to perform operations comprising:
generating an internal address based on an input address, an interleaving factor, and a number of first addressable units, wherein the interleaving factor is a value that specifies a number of bytes between each channel boundary,
wherein generating the internal address comprises:
determining a lower address value, and
determining an upper address value; and
generating, using the internal address, at least a first addressable unit address.
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