US 11,928,042 B2
Initialization and power fail isolation of a memory module in a system
Dat T. Le, Tigard, OR (US); and George Vergis, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 24, 2020, as Appl. No. 16/827,974.
Prior Publication US 2020/0226045 A1, Jul. 16, 2020
Int. Cl. G06F 11/00 (2006.01); G06F 1/30 (2006.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01); G06F 11/32 (2006.01)
CPC G06F 11/3058 (2013.01) [G06F 1/30 (2013.01); G06F 11/0772 (2013.01); G06F 11/0787 (2013.01); G06F 11/3037 (2013.01); G06F 11/327 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory module comprising:
a memory integrated circuit; and
a power management integrated circuit communicatively coupled to the memory integrated circuit, the power management integrated circuit including a voltage regulator and
a non-volatile memory to store a power fail status of the voltage regulator from a prior power cycle, the power management integrated circuit to electrically isolate the memory module dependent on the power fail status of the voltage regulator.