US 11,928,015 B1
Bus repeater and bit injector for MIL-STD-1553/1760 communications bus
Jason P. Krein, Albuquerque, NM (US); Jeremy W. Giron, Albuquerque, NM (US); Matthew S. Geuss, Albuquerque, NM (US); Robert Nevett, IV, Albuquerque, NM (US); Stephen T. Simpson, Albuquerque, NM (US); Roger Martin Kilgore, Placitas, NM (US); and Jacob Edward Leemaster, Cambridge, MA (US)
Assigned to National Technology & Engineering Solutions of Sandia, LLC, Albuquerque, NM (US)
Filed by National Technology & Engineering Solutions of Sandia, LLC, Albuquerque, NM (US)
Filed on Mar. 30, 2022, as Appl. No. 17/708,555.
Int. Cl. G06F 11/07 (2006.01); G06F 13/42 (2006.01)
CPC G06F 11/079 (2013.01) [G06F 11/0745 (2013.01); G06F 13/42 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a transceiver that is configured to receive and transmit messages by way of a communications bus that is configured as a MIL-STD-1553 or MIL-STD-1760 communications bus;
a field-programmable gate array (FPGA) that is communicatively coupled to the transceiver such that the FPGA can transmit and receive messages on the communications bus by way of the transceiver, the FPGA configured to perform acts comprising:
responsive to receiving, at the transceiver, a first signal from the communications bus, the first signal indicative of a first bit, determining whether the first bit matches a rule; and
responsive to determining that the first bit matches the rule, performing an action specified by the rule, wherein the action comprises one of:
causing the transceiver to transmit a second signal that is indicative of the first bit;
causing the transceiver to transmit a third signal that is indicative of a second bit that is different from the first bit; or
causing the transceiver to fail to transmit a signal responsive to receiving the first bit.