| CPC G03F 1/22 (2013.01) [G03F 1/24 (2013.01); G03F 1/42 (2013.01); G03F 7/2004 (2013.01); G03F 7/2022 (2013.01); G03F 9/7003 (2013.01); G03F 9/7084 (2013.01)] | 19 Claims |
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1. A method comprising:
forming a first photomask including a first mask layout region, wherein the first mask layout region includes N mask chip regions and a first mask scribe lane region surrounding each of the N mask chip regions;
forming a second photomask including a second mask layout region, wherein the second mask layout region includes M mask chip regions and a second mask scribe lane region surrounding each of the M mask chip regions;
performing a first semiconductor process including a first photolithography process using the first mask layout region of the first photomask on a semiconductor wafer; and
performing a second semiconductor process including a second photolithography process using the second mask layout region of the second photomask on the semiconductor wafer,
wherein the first photolithography process is an extreme ultraviolet (EUV) photolithography process,
the first photomask is an EUV photomask,
N is a natural number of 2 or more,
M=2*N,
wherein each of the N mask chip regions of the first photomask comprises first circuit layout patterns,
wherein each of the M mask chip regions of the second photomask comprise second circuit layout patterns,
wherein the first mask scribe lane region of the first photomask comprises first mask alignment patterns,
wherein the second mask scribe lane region of the second photomask comprises second mask alignment patterns,
wherein the semiconductor wafer comprises a semiconductor substrate, lower alignment patterns and lower circuit patterns on the semiconductor substrate, and upper alignment patterns and upper circuit patterns on the semiconductor substrate,
wherein the lower alignment patterns and the lower circuit patterns are formed by performing the first semiconductor process including the first photolithography process using the first mask layout region of the first photomask, and
wherein the upper alignment patterns and the upper circuit patterns are formed by performing the second semiconductor process including the second photolithography process using the second mask layout region of the second photomask.
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