US 11,927,628 B2
Benchmark circuit on a semiconductor wafer and method for operating the same
Chu-Feng Liao, Hsinchu (TW); Hung-Ping Cheng, Chiayi (TW); Yuan-Yao Chang, Kaohsiung County (TW); and Shuo-Wen Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jul. 16, 2021, as Appl. No. 17/378,280.
Prior Publication US 2023/0014148 A1, Jan. 19, 2023
Int. Cl. G01R 31/317 (2006.01); H01L 21/66 (2006.01)
CPC G01R 31/31722 (2013.01) [G01R 31/31723 (2013.01); G01R 31/31724 (2013.01); G01R 31/31725 (2013.01); H01L 22/34 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor wafer, comprising:
a scribe line between a first row of dies and a second row of dies; and
a first conductive contact and a second conductive contact disposed on the scribe line;
a benchmark circuit disposed on the scribe line and electrically coupled to the first conductive contact and the second conductive contact, the benchmark circuit comprising:
a first device-under-test (DUT);
a second DUT;
a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and
a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.