US 12,250,891 B2
Method of forming an integrated circuit structure including a resistive random access memory (RRAM) cell
Yaojian Leng, Vancouver, WA (US)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on Mar. 11, 2024, as Appl. No. 18/600,826.
Application 18/600,826 is a division of application No. 17/379,181, filed on Jul. 19, 2021, granted, now 12,010,932.
Claims priority of provisional application 63/208,039, filed on Jun. 8, 2021.
Prior Publication US 2024/0215464 A1, Jun. 27, 2024
Int. Cl. H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/841 (2023.02) [H10N 70/066 (2023.02); H10N 70/24 (2023.02); H10N 70/245 (2023.02); H10N 70/826 (2023.02); H10N 70/8833 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit structure including a resistive random access memory cell, the method comprising:
forming a tub opening in a dielectric region;
forming a cup-shaped bottom electrode in the tub opening, comprising:
forming a cup-shaped bottom electrode outer component in the tub opening, the cup-shaped bottom electrode outer component comprising a first metal; and
forming a cup-shaped bottom electrode inner component over the cup-shaped bottom electrode outer component, the cup-shaped bottom electrode inner comprising a second metal different than the first metal;
forming a cup-shaped insulator in an interior opening defined by the cup-shaped bottom electrode;
forming a top electrode in an interior opening defined by the cup-shaped insulator; and
forming an upper metal layer over the dielectric region, the upper metal layer including a top electrode contact in electrical contact with the top electrode,
the cup-shaped bottom electrode, the cup-shaped insulator, and the top electrode defining the resistive random access memory cell.