| CPC H10K 59/88 (2023.02) [G01R 31/2884 (2013.01); G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); H10K 71/70 (2023.02); G09G 2300/0408 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2330/12 (2013.01)] | 20 Claims | 

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               1. A display panel, comprising: 
            a base substrate, comprising a display area and a non-display area at least partially surrounding the display area; 
                a pixel array which is in the display area on the base substrate and comprises a plurality of pixel rows extending in a first direction, wherein each pixel row of the plurality of pixel rows comprises a first signal line and subpixels, and each subpixel comprises a pixel circuit, and the first signal line is configured to provide a scanning signal to the pixel circuit in the pixel row where the first signal line is located; 
                a scan driver circuit configured to provide the scanning signal to the pixel circuit and comprises a shift register and a clock signal line that are in the display area; 
                a test circuit board in the non-display area and comprising a test pad; and 
                a test lead in the non-display area and electrically connected with the test pad, wherein the first signal line comprises a first part in the display area, and a second part that is in the non-display area and is connected with the first part, the first part extends substantially along the first direction, and the second part is connected with the first part; 
                before the display panel is tested, the first signal line and the test lead are arranged in different layers and insulated from each other; when the display panel is tested, the test lead and the second part of the first signal line are connected to each other, and the test circuit board is configured to acquire a test signal from the first signal line through the test pad and the test lead. 
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