US 12,250,866 B2
Display motherboard and method for manufacturing display substrate
Yongjie Song, Beijing (CN); Siyu Wang, Beijing (CN); Shun Zhang, Beijing (CN); Yi Zhang, Beijing (CN); Fengli Ji, Beijing (CN); Yuanqi Zhang, Beijing (CN); Yi Qu, Beijing (CN); and Yan Huang, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/631,136
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Apr. 9, 2021, PCT No. PCT/CN2021/086097
§ 371(c)(1), (2) Date Jan. 28, 2022,
PCT Pub. No. WO2021/238429, PCT Pub. Date Dec. 2, 2021.
Claims priority of application No. 202010465150.5 (CN), filed on May 27, 2020.
Prior Publication US 2022/0262889 A1, Aug. 18, 2022
Int. Cl. H10K 59/88 (2023.01); H01L 27/12 (2006.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/122 (2023.01); H10K 59/131 (2023.01); H10K 59/80 (2023.01); H10K 71/00 (2023.01)
CPC H10K 59/88 (2023.02) [H01L 27/124 (2013.01); H10K 59/1201 (2023.02); H10K 59/131 (2023.02); H10K 59/80515 (2023.02); H10K 59/1213 (2023.02); H10K 59/122 (2023.02); H10K 71/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A display motherboard, comprising:
a substrate, the substrate comprising a valid area and an edge area on at least one side of the valid area, the valid area comprising a plurality of panel areas and a to-be-cut area, the to-be-cut area separating the plurality of panel areas from each other and separating the edge area from a panel area adjacent to the edge area, and the panel area comprising a display area and a frame area surrounding the display area;
a plurality of first power lines on the substrate, each display area and the edge area being provided with a plurality of the first power lines, and the first power line extending along a first direction; and
a plurality of first display electrodes in each display area and a plurality of virtual electrodes in the edge area, the plurality of first display electrodes and the plurality of virtual electrodes being in the same layer,
wherein an orthographic projection of each of the plurality of first display electrodes on the substrate overlaps an orthographic projection of at most one first power line, and an orthographic projection of each of the plurality of virtual electrodes on the substrate overlaps orthographic projections of at least two first power lines on the substrate.