US 12,250,834 B2
Power device and manufacturing method thereof
Kuo-Hsuan Lo, Taoyuan (TW); Chien-Hao Huang, Penghu (TW); Chu-Feng Chen, Hsibchu (TW); and Wu-Te Weng, Hsibchu (TW)
Assigned to RICHTEK TECHNOLOGY CORPORATION, Zhubei (TW)
Filed by Richtek Technology Corporation, Zhubei (TW)
Filed on May 5, 2022, as Appl. No. 17/737,231.
Claims priority of application No. 110129608 (TW), filed on Aug. 11, 2021.
Prior Publication US 2023/0046174 A1, Feb. 16, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 21/765 (2006.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01); H10D 62/17 (2025.01); H10D 64/00 (2025.01); H10D 84/00 (2025.01)
CPC H10D 64/111 (2025.01) [H01L 21/765 (2013.01); H10D 30/0281 (2025.01); H10D 30/65 (2025.01); H10D 62/393 (2025.01); H10D 84/151 (2025.01); H10D 30/0285 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A power device, comprising:
a semiconductor layer, which is formed on a substrate, and has a top surface;
a well having a first conductivity type, which is formed in the semiconductor layer, wherein the well is located below and in contact with the top surface;
a body region having a second conductivity type, which is formed in the semiconductor layer, wherein the body region is located below and in contact with the top surface, and wherein the body region is in contact with the well in a channel direction;
a gate, which is formed on the top surface, wherein a part of the body region is located vertically below and in contact with the gate, to serve as an inversion current channel in an ON operation of the power device, and wherein a part of the well which is in contact with the body region is located vertically below the gate, to serve as a drift current channel in the ON operation of the power device;
a source and a drain having the first conductivity type, which are formed below and in contact with the top surface, wherein the source and the drain are located below and outside two sides of the gate respectively, wherein the side of the gate which is closer to the source is a source side and the side of the gate which is closer to the drain is a drain side, and wherein the source is located in the body region, and the drain is located in the well outside the drain side;
a first salicide block (SAB) layer, which is formed on the top surface and which is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer; and
a second SAB layer, which is formed vertically above and in contact with the first SAB layer;
wherein the substrate has a low voltage region and a high voltage region, wherein the power device is formed in the high voltage region;
wherein a plurality of metal oxide semiconductor (MOS) devices are formed in the low voltage region;
wherein the first SAB layer is formed in the low voltage region and the high voltage region; and
wherein the second SAB layer is formed in the high voltage region and is not located in the low voltage region.