| CPC H10D 64/01 (2025.01) [H01L 21/31155 (2013.01); H01L 21/32053 (2013.01); H10D 64/015 (2025.01); H10D 64/021 (2025.01)] | 20 Claims |
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1. A method of manufacturing a semiconductor device structure, comprising:
providing a substrate having a surface which is defined as an upper surface of the substrate;
forming a first gate structure on and in direct contact with the surface;
forming a second gate structure on and in direct contact with the surface, wherein the first gate structure and the second gate structure are spaced apart from each other to form a trench therebetween;
forming a first well region in the substrate and between the first gate structure and the second gate structure, wherein the first well region is formed below the surface of the substrate at a position that a top surface of the first well region is coplanar with the surface of the substrate;
forming a conductive contact within the trench between the first gate structure and the second gate structure;
forming a first structure within the first well region at a position that a top surface of the first structure is below the surface of the substrate, wherein the first structure tapers away from a bottom portion of the conductive contact; and
forming a first layer, wherein the first layer has a bottom portion embedded in the substrate and two vertical walls upwardly extended from the bottom portion to receive the conductive contact between the two vertical walls, wherein a bottom surface of the bottom portion of the first layer is in contact with the top surface of the first structure, wherein a width of the bottom portion of the first layer is larger than a length of the top surface of the first structure.
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