US 12,250,830 B2
3D semiconductor memory devices and structures
Zvi Or-Bach, Haifa (IL); and Jin-Woo Han, San Jose, CA (US)
Assigned to Monolithic 3D Inc., Klamath Falls, OR (US)
Filed by Monolithic 3D Inc., Klamath Falls, OR (US)
Filed on Mar. 1, 2024, as Appl. No. 18/593,727.
Application 18/593,727 is a continuation in part of application No. 18/385,383, filed on Oct. 31, 2023.
Application 18/385,383 is a continuation in part of application No. 17/367,385, filed on Jul. 4, 2021, granted, now 11,937,422.
Application 17/367,385 is a continuation in part of application No. 16/786,060, filed on Feb. 10, 2020, granted, now 11,114,427, issued on Sep. 7, 2021.
Application 16/786,060 is a continuation in part of application No. 16/377,238, filed on Apr. 7, 2019, granted, now 10,622,365, issued on Apr. 14, 2020.
Application 16/377,238 is a continuation in part of application No. 15/911,071, filed on Mar. 2, 2018, granted, now 10,297,599, issued on May 21, 2019.
Application 15/911,071 is a continuation in part of application No. 15/344,562, filed on Nov. 6, 2016, granted, now 9,953,994, issued on Apr. 24, 2018.
Application 18/593,727 is a continuation in part of application No. 16/797,231, filed on Feb. 21, 2020.
Application 16/797,231 is a continuation in part of application No. 16/224,674, filed on Dec. 18, 2018, abandoned.
Application 16/224,674 is a continuation in part of application No. 15/761,426, granted, now 10,515,981, issued on Dec. 24, 2019, previously published as PCT/US2016/052726, filed on Sep. 21, 2016.
Claims priority of provisional application 62/297,857, filed on Feb. 20, 2016.
Claims priority of provisional application 62/269,950, filed on Dec. 19, 2015.
Claims priority of provisional application 62/258,433, filed on Nov. 21, 2015.
Claims priority of provisional application 62/252,448, filed on Nov. 7, 2015.
Claims priority of provisional application 62/221,618, filed on Sep. 21, 2015.
Prior Publication US 2024/0215274 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 80/00 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H10B 80/00 (2023.02) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors;
a first metal layer overlaying said first single crystal layer;
a second metal layer overlaying said first metal layer;
a plurality of second transistors disposed atop said second metal layer;
a third metal layer disposed atop said plurality of second transistors; and
a memory array comprising word-lines and memory cells,
wherein said memory array comprises at least four memory mini arrays,
wherein at least one of said plurality of second transistors comprises a metal gate,
wherein each of said memory cells comprises at least one of said plurality of second transistors,
wherein said memory control circuit comprises at least one Look Up Table circuit (“LUT”), and
wherein said device comprises a hybrid bonding layer.