US 12,250,828 B2
Semiconductor structure and fabrication method thereof
John H Zhang, Altamont, NY (US); Brian Li Ji, Mount Kisco, NY (US); Yanzun Li, Lagrangeville, NY (US); and Devendra K Sadana, Pleasantville, NY (US)
Assigned to HEFECHIP CORPORATION LIMITED, Sai Ying Pun (HK)
Filed by HeFeChip Corporation Limited, Sai Ying Pun (HK)
Filed on Mar. 1, 2022, as Appl. No. 17/683,382.
Prior Publication US 2023/0284458 A1, Sep. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 61/00 (2023.01); H01L 49/02 (2006.01); H10B 12/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01)
CPC H10B 61/22 (2023.02) [H01L 28/75 (2013.01); H01L 28/92 (2013.01); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02); H10B 12/00 (2023.02); H10N 50/01 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate comprising a doped silicon substrate, a buried oxide layer on the doped silicon substrate, and a silicon device layer on the buried oxide layer;
a capacitor comprising an inner electrode and a node dielectric layer in a trench of the substrate, wherein the inner electrode and the node dielectric layer penetrate through the buried oxide layer and extend into the doped silicon substrate;
a select transistor in the silicon device layer and in proximity to the capacitor, wherein the silicon device layer forms a silicon fin;
an embedded contact atop the capacitor to electrically couple a doped region of the select transistor with the inner electrode of the capacitor, wherein the embedded contact comprises a metallic layer wrapped around by a silicide layer, and wherein a portion of the silicide layer is interposed between the metallic layer and the inner electrode, wherein the inner electrode comprises a doped polysilicon layer and a TiN layer between the node dielectric layer and the doped polysilicon layer, wherein the TiN layer protrudes from a top surface of the doped polysilicon layer, and wherein an upper end of the node dielectric layer, an upper end of the TiN layer, and the top surface of the doped polysilicon layer form a step structure around an upper portion of the trench, and wherein the silicide layer completely covers the step structure;
a first dielectric layer around the select transistor;
a second dielectric layer covering the first dielectric layer and the select transistor;
a contact plug penetrating through the second dielectric layer and the first dielectric layer and being in direct contact with the embedded contact; and
a memory stack electrically connected to the contact plug, wherein the memory stack comprises a magnetic tunnel junction (MTJ) element.