CPC H10B 61/00 (2023.02) [G11C 11/161 (2013.01); H10N 50/01 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02)] | 20 Claims |
1. A memory device, comprising:
a magnetic tunnel junction pillar above a bottom electrode, the bottom electrode including a metal-oxide region in contact with a first portion of the magnetic tunnel junction pillar and a metal region surrounding the metal-oxide region; and
a sidewall spacer along sidewalls of the magnetic tunnel junction pillar, the metal region being in contact with a bottom surface of the sidewall spacer and a second portion of the magnetic tunnel junction pillar.
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