US 12,250,826 B2
Integrated circuit device and method for fabricating the same
Yuan-Jen Lee, Hsinchu (TW); Harry-Hak-Lay Chuang, Hsinchu County (TW); Tien-Wei Chiang, Taipei (TW); Hung Cho Wang, Taipei (TW); Kuei-Hung Shen, Hsinchu (TW); and Sheng-Huang Huang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 30, 2021, as Appl. No. 17/460,885.
Prior Publication US 2023/0065850 A1, Mar. 2, 2023
Int. Cl. H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC H10B 61/00 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a substrate;
a memory cell over the substrate, wherein the memory cell comprises a bottom electrode, a resistance switching element over the bottom electrode, a top electrode over the resistance switching element;
a magnetic shielding element around the memory cell, wherein a top of the magnetic shielding element is lower than a top surface of the top electrode, and the magnetic shielding element is in contact with the bottom electrode;
an interlayer dielectric layer surrounding the memory cell and the magnetic shielding element; and
a metallization pattern in the interlayer dielectric layer and connected to the top electrode.