US 12,250,824 B2
Ferroelectric memory cell
Chung-Liang Cheng, Changhua (TW); and Huang-Lin Chao, Hillsboro, OR (US)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 16, 2023, as Appl. No. 18/511,461.
Application 18/511,461 is a continuation of application No. 17/472,479, filed on Sep. 10, 2021, granted, now 11,871,581.
Claims priority of provisional application 63/166,125, filed on Mar. 25, 2021.
Prior Publication US 2024/0090232 A1, Mar. 14, 2024
Int. Cl. H01L 29/423 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01); H10B 53/00 (2023.01); H10B 53/10 (2023.01); H10B 53/20 (2023.01)
CPC H10B 53/20 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 29/42392 (2013.01); H10B 51/10 (2023.02); H10B 51/20 (2023.02); H10B 53/00 (2023.02); H10B 53/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a transistor comprising a source/drain (S/D) region and a gate structure on a front side of the S/D region; and
a ferroelectric capacitor on a back side of the S/D region.