| CPC H10B 51/20 (2023.02) [H10B 43/27 (2023.02); H10B 51/30 (2023.02)] | 20 Claims |
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1. A manufacturing method of a three-dimensional memory device, comprising:
providing a first stacking structure and a second stacking structure on a substrate, wherein the first stacking structure and the second stacking structure are laterally spaced apart from each other, and respectively comprise alternately stacked conductive layers and insulating layers;
forming isolation pillars across a spacing between the first stacking structure and the second stacking structure, wherein the isolation pillars laterally protrude into the conductive layers and the insulating layers of the first stacking structure and the second stacking structure, and cell regions are respectively enclosed by adjacent ones of the isolation pillars, the first stacking structure and the second stacking structure; and
forming gate dielectric layers, channel layers and pairs of conductive pillars in the cell regions, wherein each of the channel layers is surrounded by one of the gate dielectric layers, and each pair of the conductive pillars are surrounded by and separately in contact with one of the channel layers.
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