US 12,250,821 B2
Electronic devices including pillars in array regions and non-array regions
S M Istiaque Hossain, Boise, ID (US); Christopher J. Larsen, Boise, ID (US); Anilkumar Chandolu, Boise, ID (US); Wesley O. McKinsey, Nampa, ID (US); Tom J. John, Boise, ID (US); Arun Kumar Dhayalan, Boise, ID (US); and Prakash Rau Mokhna Rau, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 20, 2023, as Appl. No. 18/391,442.
Application 18/391,442 is a continuation of application No. 17/806,829, filed on Jun. 14, 2022, granted, now 11,871,575.
Application 17/806,829 is a continuation of application No. 16/851,638, filed on Apr. 17, 2020, granted, now 11,387,245, issued on Jul. 12, 2022.
Prior Publication US 2024/0130132 A1, Apr. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/35 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/20 (2023.01)
CPC H10B 43/35 (2023.02) [H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
two or more decks adjacent to a source, the two or more decks comprising an array region and one or more non-array regions and comprising:
memory pillars in at least a lower deck and an upper deck of the two or more decks of the array region, the memory pillars extending from the upper deck to the source; and
dummy pillars in the upper deck of the one or more non-array regions, the lower deck of the one or more non-array regions lacking dummy pillars.